Required Skills / Qualifications:
- BS degree
- Minimum of 2 years" experience In CMOS mixed-signal and analog IC design
Preferred Skills / Qualifications:
- Knowledge of transistor-level schematic design and simulation
- Knowledge of semiconductor processes
- Excellent written and oral communication
- Experienced with Virtuoso and Caliber
- Experienced performing integrated circuit physical design (layout)
- Working experience in using spectrum analyzers, oscilloscopes, signal generators, and other lab equipment, to validate analog designs
- Familiar with digital IC design using Verilog
- Ability to analyze data in Mathcad, MATLAB, or similar tools
- Ability to solve complex design problems
- Laboratory functional test of new Readout ICs
- Laboratory characterization of Readout IC sand Focal Plane Arrays (FPAs)
- Transistor-level analog circuit design
- Mixed-signal integrated circuit layout
- Circuit-level and mixed-mode simulation and verification
- Data analysis and report generation
- Documentation of design, verification, and testing
- Upon offer of employment, the individual will be subject to background check and a drug screen.
Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct, and Aleron?s strategic partner, SDI) are Equal Employment Opportunity and Affirmative Action Employers. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender identity, sexual orientation, national origin, genetic information, sex, age, disability, veteran status, or any other legally protected basis. The Aleron companies welcome and encourage applications from diverse candidates, including people with disabilities. Accommodations are available upon request for applicants taking part in all aspects of the selection process.
Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status.