Required Skills / Qualifications:
- Bachelor"s Degree(BSEE)
- Minimum of 5 years" experience in VHDL logic design
- Minimum of 5 years" experience with generating design documents including specifications, user's manuals and test plans.
- Minimum of 5 years" Physical testing experience including lab measurements (oscilloscope, digital logic analyzer), defining test setups, in-circuit debugging.
Preferred Skills / Qualifications:
- Master"s Degree (MSEE)
- ModelSim or QuestaSim experience.
- Serial communication protocols (UART, SPI, I2C, 1-Wire, Ethernet, SpaceWire),
- Fixed point mathematic fundamentals, Static Timing Analysis and Timing Closure (setup and hold, slack, skew.),
- Asynchronous Clock Domain crossing and general metastability mitigation techniques,
- Test-bench development, including timing accurate bus functional models, complete functional coverage.
- Capable of understanding and adhering to department design standards.
- Ability to work in an Agile project format, team based environment, including Jira and Git environments.
- Upon offer of employment, the individual will be subject to a background check and a drug screen.
Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct, and Aleron's strategic partner, SDI) are Equal Employment Opportunity and Affirmative Action Employers. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender identity, sexual orientation, national origin, genetic information, sex, age, disability, veteran status, or any other legally protected basis. The Aleron companies welcome and encourage applications from diverse candidates, including people with disabilities. Accommodations are available upon request for applicants taking part in all aspects of the selection process.
Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status.